Neetha Consulting LLC is hiring: Physical Design Engineer
- Cupertino, CA, USA
- Full-time, 40 hours/week, Permanent position
Job Title:
Physical Design EngineerSalary Range:
$125,000 – $145,000 per year (commensurate with experience)Location:
USAJob Duration:
40 hours/week, permanent position, full-timeJob Duties:
- Conceptualize, design, and productize advanced RTL to GDS implementations through ASIC design flow.
- Lead the physical design closure process including floorplanning, placement, clock tree synthesis, routing, and optimization.
- Develop efficient IC block layouts optimized for area, timing, and power at advanced technology nodes (e.g., TSMC N5/N4P/N3).
- Drive implementation of high-performance, low-power, manufacturable designs.
- Perform synthesis, pre-layout STA, SDC constraints development, bump placement, power planning, MV design techniques, and UPF.
- Apply timing closure techniques: clock skew balancing, delay optimization, OCV handling, and ECO management.
- Conduct power and area optimization using Multi-Vt, clock gating, and power-aware synthesis.
- Manage post-layout STA, functional/timing ECOs, and high-frequency IP designs closure.
- Ensure physical verification (DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff) compliance with foundry sign-off standards.
- Collaborate with cross-functional teams to resolve design and manufacturing issues.
- Drive scripting and automation (Python, Perl, TCL) to enhance design efficiency.
- Use EDA tools (Innovus, ICCII, Fusion Compiler, Tempus, PrimeTime) for implementation and signoff readiness.
Other Responsibilities:
- Mentor junior engineers and review design outputs.
- Document physical design flows, constraints, and reports.
- Implement and improve methodologies, workflows, and tools for better process quality and efficiency.
